Invention Grant
- Patent Title: Wiring layout decision method of integrated circuit
- Patent Title (中): 集成电路接线布局决策方法
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Application No.: US12588995Application Date: 2009-11-04
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Publication No.: US08209651B2Publication Date: 2012-06-26
- Inventor: Shinji Yokogawa , Hideaki Tsuchiya
- Applicant: Shinji Yokogawa , Hideaki Tsuchiya
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2008-287935 20081011
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A wiring layout method includes designing a layout of a power wiring for an integrated circuit; designing a layout of plural signal wirings for the integrated circuit; comparing the signal frequency; classifying the signal wirings; calculating an evaluation value of a temperature rise; and modifying the layouts of the integrated circuit.
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