Invention Grant
US08211716B2 Manufacturing method of a semiconductor device, a semiconductor wafer, and a test method 有权
半导体器件的制造方法,半导体晶片和测试方法

Manufacturing method of a semiconductor device, a semiconductor wafer, and a test method
Abstract:
The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing.
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