Invention Grant
- Patent Title: Wafer level stack die package
- Patent Title (中): 晶圆级堆叠封装
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Application No.: US13323979Application Date: 2011-12-13
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Publication No.: US08211747B2Publication Date: 2012-07-03
- Inventor: Dan Kinzer , Yong Liu , Stephen Martin
- Applicant: Dan Kinzer , Yong Liu , Stephen Martin
- Applicant Address: US CA San Jose
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
This document discusses, among other things, apparatus and methods for an IC package including first and a second discrete components fabricated into a semiconductor substrate. The first and second discrete components can be adjacent to one another in the semiconductor substrate, and an integrated circuit die can be mounted on the semiconductor substrate and coupled to the first and second discrete components.
Public/Granted literature
- US20120088331A1 WAFER LEVEL STACK DIE PACKAGE Public/Granted day:2012-04-12
Information query
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