Invention Grant
- Patent Title: Systems and methods for low profile die package
- Patent Title (中): 薄型芯片封装的系统和方法
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Application No.: US11511175Application Date: 2006-08-28
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Publication No.: US08211748B2Publication Date: 2012-07-03
- Inventor: Hun K. Lee , Sai M. Lee , Li C. Tai
- Applicant: Hun K. Lee , Sai M. Lee , Li C. Tai
- Applicant Address: SG Singapore
- Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor integrated circuit (IC) device is defined by a low-profile package without a die attach pad (DAP). In place of the DAP, an adhesive element is used to retain a die relative to a lead frame during processing. In one example, a method of manufacturing the device includes sealing the lead frame on one side using an adhesive tape and exposing a portion of the tape within a die attach region. The die is secured onto the tape adhesive and held in place during subsequent processing, such as a wire bonding procedure to couple the die to external portions of the frame.
Public/Granted literature
- US20080048302A1 Systems and methods for low profile die package Public/Granted day:2008-02-28
Information query
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