Invention Grant
- Patent Title: Integrated circuit package system with waferscale spacer
- Patent Title (中): 集成电路封装系统,带有硅片间隔器
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Application No.: US11465706Application Date: 2006-08-18
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Publication No.: US08211749B2Publication Date: 2012-07-03
- Inventor: Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
- Applicant: Sang-Ho Lee , Jong-Woo Ha , Soo-San Park
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Agent Mikio Ishimaru; Stanley Chang
- Main IPC: H01L21/50
- IPC: H01L21/50

Abstract:
An integrated circuit packaging system is provided including forming a first device wafer having a first backside and a first active side; forming a waferscale spacer wafer having a waferscale spacer and a first opening; mounting the waferscale spacer wafer on the first backside; and singulating an first integrated circuit die having the waferscale spacer from the first device wafer having the first backside with the waferscale spacer wafer thereon.
Public/Granted literature
- US20080042245A1 INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WAFERSCALE SPACER Public/Granted day:2008-02-21
Information query
IPC分类: