Invention Grant
US08211760B2 Method for producing a transistor gate with sub-photolithographic dimensions
有权
用于制造具有次光刻尺寸的晶体管栅极的方法
- Patent Title: Method for producing a transistor gate with sub-photolithographic dimensions
- Patent Title (中): 用于制造具有次光刻尺寸的晶体管栅极的方法
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Application No.: US13084820Application Date: 2011-04-12
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Publication No.: US08211760B2Publication Date: 2012-07-03
- Inventor: Nathan Ray Perkins , Timothy Arthur Valade , Albert William Wang
- Applicant: Nathan Ray Perkins , Timothy Arthur Valade , Albert William Wang
- Applicant Address: SG Singapore
- Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L21/338
- IPC: H01L21/338 ; H01L21/336 ; H01L21/28 ; H01L21/31
Abstract:
A method of fabricating a semiconductor device is disclosed. The method comprises patterning a photoresist over a compound semiconductor substrate; reducing a width of the photoresist; forming a hardmask over the substrate and not over the photoresist; removing the photoresist; etching to form and opening down to the substrate; forming a gate in the opening; and removing the hardmask except beneath the gate.
Public/Granted literature
- US20110250743A1 METHOD FOR PRODUCING A TRANSISTOR GATE WITH SUB-PHOTOLITHOGRAPHIC DIMENSIONS Public/Granted day:2011-10-13
Information query
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