Invention Grant
US08211763B2 Methods of forming vertical field effect transistors, vertical field effect transistors, and DRAM cells
有权
形成垂直场效应晶体管，垂直场效应晶体管和DRAM单元的方法
- Patent Title: Methods of forming vertical field effect transistors, vertical field effect transistors, and DRAM cells
- Patent Title (中): 形成垂直场效应晶体管，垂直场效应晶体管和DRAM单元的方法
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Application No.: US13036725Application Date: 2011-02-28
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Publication No.: US08211763B2Publication Date: 2012-07-03
- Inventor: Larson D. Lindholm , David K. Hwang
- Applicant: Larson D. Lindholm , David K. Hwang
- Applicant Address: US ID Boise
- Assignee: Micron Technologies, Inc.
- Current Assignee: Micron Technologies, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L21/8242 ; H01L21/336 ; H01L29/78
Abstract:
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.
Public/Granted literature
- US20110140187A1 Methods of Forming Vertical Field Effect Transistors, Vertical Field Effect Transistors, And DRAM Cells Public/Granted day:2011-06-16
Information query
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