Invention Grant
US08211769B2 Method for forming junctions of vertical cells in semiconductor device
有权
在半导体器件中形成垂直电池结的方法
- Patent Title: Method for forming junctions of vertical cells in semiconductor device
- Patent Title (中): 在半导体器件中形成垂直电池结的方法
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Application No.: US13025586Application Date: 2011-02-11
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Publication No.: US08211769B2Publication Date: 2012-07-03
- Inventor: Bo-Mi Lee
- Applicant: Bo-Mi Lee
- Applicant Address: KR Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2010-0040901 20100430
- Main IPC: H01L21/8242
- IPC: H01L21/8242

Abstract:
A method for fabricating a semiconductor device includes forming a plurality of active regions that are separated from each other by a plurality of trenches, respectively, wherein the trenches are formed by etching a substrate, forming an insulation layer having openings that each expose a portion of a first sidewall of each active region, forming a filling layer which fills the openings, forming a diffusion control layer over a substrate structure including the filling layer, and forming a junction on a portion of the first sidewall of each active region.
Public/Granted literature
- US20110269279A1 METHOD FOR FORMING JUNCTIONS OF VERTICAL CELLS IN SEMICONDUCTOR DEVICE Public/Granted day:2011-11-03
Information query
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