Invention Grant
- Patent Title: Method for forming isolation layer in semiconductor device
- Patent Title (中): 在半导体器件中形成隔离层的方法
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Application No.: US11958381Application Date: 2007-12-17
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Publication No.: US08211779B2Publication Date: 2012-07-03
- Inventor: Byung-Soo Eun
- Applicant: Byung-Soo Eun
- Applicant Address: KR Icheon-si
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Kilpatrick Townsend & Stockton LLP
- Priority: KR10-2007-0091195 20070907
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/8238 ; H01L21/336 ; H01L21/311 ; H01L21/469
Abstract:
Provided is a method for forming an isolation layer in a semiconductor device. In the method, a trench is formed in a semiconductor substrate, and a liner layer is formed on an exposed surface of the trench. A flowable insulation layer is formed to fill the trench. The flowable insulation layer is recessed. A buffer layer is formed on a portion of the liner layer that is formed on a sidewall of the trench and exposed after the flowable insulation layer is recessed. The buffer layer is etched to smoothen a rough portion of the liner layer that is formed when the flowable insulation layer is recessed. A buried insulation layer is deposited in the trench.
Public/Granted literature
- US20090068816A1 METHOD FOR FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE Public/Granted day:2009-03-12
Information query
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