Invention Grant
US08211804B2 Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole
有权
形成具有垂直剖面的孔的方法和具有垂直孔的半导体器件
- Patent Title: Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole
- Patent Title (中): 形成具有垂直剖面的孔的方法和具有垂直孔的半导体器件
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Application No.: US13025410Application Date: 2011-02-11
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Publication No.: US08211804B2Publication Date: 2012-07-03
- Inventor: Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
- Applicant: Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Onello & Mello, LLP
- Priority: KR10-2010-0013113 20100212
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.
Public/Granted literature
- US20110201203A1 METHODS OF FORMING A HOLE HAVING A VERTICAL PROFILE AND SEMICONDUCTOR DEVICES HAVING A VERTICAL HOLE Public/Granted day:2011-08-18
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