Invention Grant
- Patent Title: Method of fabricating integrated circuit with small pitch
- Patent Title (中): 制造小间距集成电路的方法
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Application No.: US11846900Application Date: 2007-08-29
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Publication No.: US08211806B2Publication Date: 2012-07-03
- Inventor: Chia-Wei Wu , Ling-Wu Yang
- Applicant: Chia-Wei Wu , Ling-Wu Yang
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX International Co., Ltd.
- Current Assignee: MACRONIX International Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Main IPC: H01L21/302
- IPC: H01L21/302

Abstract:
A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.
Public/Granted literature
- US20090061624A1 METHOD OF FABRICATING INTEGRATED CIRCUIT WITH SMALL PITCH Public/Granted day:2009-03-05
Information query
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