Invention Grant
- Patent Title: Wiring substrate and semiconductor package
- Patent Title (中): 接线基板和半导体封装
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Application No.: US12471802Application Date: 2009-05-26
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Publication No.: US08212151B2Publication Date: 2012-07-03
- Inventor: Takayuki Yamamoto
- Applicant: Takayuki Yamamoto
- Applicant Address: JP Nagano-shi, Nagano
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-shi, Nagano
- Agency: Drinker Biddle & Reath LLP
- Priority: JP2008-138910 20080528
- Main IPC: H05K1/00
- IPC: H05K1/00

Abstract:
A wiring substrate includes: an insulating layer; a wiring formed on the insulating layer; and a solder resist layer formed on the insulating layer so as to cover at least a portion of the wiring, the solder resist layer being constituted by a plurality of layers, wherein the plurality of layers contain fillers of different grain diameters, a layer thickness of an innermost layer for constituting the plurality of layers is thicker than a layer thickness of the wiring, and a grain diameter of the filler contained in the innermost layer is smaller than a shortest interval between adjacent lines of the wiring.
Public/Granted literature
- US20090296364A1 WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE Public/Granted day:2009-12-03
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