Invention Grant
US08212253B2 Shallow junction formation and high dopant activation rate of MOS devices
有权
浅结点形成和MOS器件的高掺杂剂激活率
- Patent Title: Shallow junction formation and high dopant activation rate of MOS devices
- Patent Title (中): 浅结点形成和MOS器件的高掺杂剂激活率
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Application No.: US13228182Application Date: 2011-09-08
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Publication No.: US08212253B2Publication Date: 2012-07-03
- Inventor: Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
- Applicant: Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/167
- IPC: H01L29/167 ; H01L29/26 ; H01L29/24 ; H01L21/22
Abstract:
A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.
Public/Granted literature
- US20110316079A1 Shallow Junction Formation and High Dopant Activation Rate of MOS Devices Public/Granted day:2011-12-29
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