Invention Grant
US08212294B2 Structure having silicon CMOS transistors with column III-V transistors on a common substrate
有权
具有在同一基板上具有列III-V晶体管的硅CMOS晶体管的结构
- Patent Title: Structure having silicon CMOS transistors with column III-V transistors on a common substrate
- Patent Title (中): 具有在同一基板上具有列III-V晶体管的硅CMOS晶体管的结构
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Application No.: US12695518Application Date: 2010-01-28
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Publication No.: US08212294B2Publication Date: 2012-07-03
- Inventor: William E. Hoke , Jeffrey R. LaRoche
- Applicant: William E. Hoke , Jeffrey R. LaRoche
- Applicant Address: US MA Waltham
- Assignee: Raytheon Company
- Current Assignee: Raytheon Company
- Current Assignee Address: US MA Waltham
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- Main IPC: H01L27/085
- IPC: H01L27/085
Abstract:
A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is and wherein the crystallographic orientation of the silicon layer is . In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the silicon layer.
Public/Granted literature
- US20110180857A1 STRUCTURE HAVING SILICON CMOS TRANSISTORS WITH COLUMN III-V TRANSISTORS ON A COMMON SUBSTRATE Public/Granted day:2011-07-28
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