Invention Grant
US08212322B2 Techniques for enabling multiple Vt devices using high-K metal gate stacks
有权
使用高K金属栅极堆叠实现多个Vt器件的技术
- Patent Title: Techniques for enabling multiple Vt devices using high-K metal gate stacks
- Patent Title (中): 使用高K金属栅极堆叠实现多个Vt器件的技术
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Application No.: US12720354Application Date: 2010-03-09
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Publication No.: US08212322B2Publication Date: 2012-07-03
- Inventor: Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
- Applicant: Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Vazken Alexanian; Michael J. Chang, LLC
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/8244
Abstract:
Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
Public/Granted literature
- US20100164011A1 Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks Public/Granted day:2010-07-01
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