Invention Grant
- Patent Title: Process for improving the reliability of interconnect structures and resulting structure
- Patent Title (中): 提高互连结构和结构结构可靠性的方法
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Application No.: US12879770Application Date: 2010-09-10
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Publication No.: US08212330B2Publication Date: 2012-07-03
- Inventor: Hsien-Wei Chen , Jian-Hong Lin , Tzu-Li Lee
- Applicant: Hsien-Wei Chen , Jian-Hong Lin , Tzu-Li Lee
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
Public/Granted literature
- US20100327456A1 Process for Improving the Reliability of Interconnect Structures and Resulting Structure Public/Granted day:2010-12-30
Information query
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