Invention Grant
US08212361B2 Semiconductor die package including multiple dies and a common node structure
有权
半导体管芯封装包括多个管芯和一个共同的节点结构
- Patent Title: Semiconductor die package including multiple dies and a common node structure
- Patent Title (中): 半导体管芯封装包括多个管芯和一个共同的节点结构
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Application No.: US12575641Application Date: 2009-10-08
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Publication No.: US08212361B2Publication Date: 2012-07-03
- Inventor: Rajeev Joshi , Venkat Iyer , Jonathan Klein
- Applicant: Rajeev Joshi , Venkat Iyer , Jonathan Klein
- Applicant Address: US ME South Portland
- Assignee: Fairchild Semiconductor Corporation
- Current Assignee: Fairchild Semiconductor Corporation
- Current Assignee Address: US ME South Portland
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.
Public/Granted literature
- US20100090331A1 SEMICONDUCTOR DIE PACKAGE INCLUDING MULTIPLE DIES AND A COMMON NODE STRUCTURE Public/Granted day:2010-04-15
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