Invention Grant
- Patent Title: PLL circuit
- Patent Title (中): PLL电路
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Application No.: US12662042Application Date: 2010-03-29
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Publication No.: US08212596B2Publication Date: 2012-07-03
- Inventor: Atsushi Furuta
- Applicant: Atsushi Furuta
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2009-100024 20090416
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
There is provided a PLL circuit including a first loop filter and a second loop filter, which includes a current signal generation circuit that includes a first output driver that generates a first current signal to be output to the first loop filter and a second output driver that generates a second current signal to be output to the second loop filter, and a control circuit that selects which of the first output driver and the second output driver is to be activated.
Public/Granted literature
- US20100264964A1 Pll circuit Public/Granted day:2010-10-21
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