A clock output from a quartz oscillator is input to a timing generator via a spread spectrum clock generator that spreads the spectrum of the clock. The clock is multiplexed by a phase locked loop to generate pixel clocks having the same frequency as a pixel frequency. The pixel clock is input to a delay locked loop, which generates a multi-layer clock by dividing each cycle of the pixel clock by 60. Clock generating units select a required phase from the multi-layer clock, thereby generating a timing signal. The phase, the pulse width, and the output period of the timing signal are controlled as desired by setting appropriate values to a register.