A circuit arrangement for protecting an electronic device from damage upon a fault. The circuit arrangement includes at least one first terminal, at least one second terminal, a first interface and a second interface, a fault detection circuit region, a fault signal processing circuit region, and a disconnection circuit region. The at least one first terminal is coupled to the at least one second terminal in a fault-free state, the fault detection circuit region is coupled to the fault signal processing circuit region, the fault signal processing circuit region is coupled to the disconnection circuit region, the disconnection circuit region is configured to disconnect at least one of the at least one first terminal and the at least one second terminal, and the fault detection circuit region, the first and second interfaces, and the disconnection circuit region are configured to be compatible with another different fault signal processing circuit region.