Invention Grant
- Patent Title: Vertical transistor memory cell and array
- Patent Title (中): 垂直晶体管存储单元和阵列
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Application No.: US12632394Application Date: 2009-12-07
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Publication No.: US08213226B2Publication Date: 2012-07-03
- Inventor: Eric Carman
- Applicant: Eric Carman
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wilmer Cutler Pickering Hale and Dorr LLP
- Main IPC: G11C11/34
- IPC: G11C11/34
Abstract:
A semiconductor device along with circuits including the same and methods of operating the same are described. The device includes an electrically floating body region and a gate disposed about a first portion of the body region. The device includes a source region adjoining a second portion of the body region, the second portion adjacent the first portion and separating the source region from the first portion. The device includes a drain region adjoining a third portion of the body region, the third portion adjacent the first portion and separating the drain region from the first portion, wherein the source and drain regions are opposing.
Public/Granted literature
- US20100142294A1 Vertical Transistor Memory Cell and Array Public/Granted day:2010-06-10
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