Invention Grant
US08213227B2 4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure
有权
具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元
- Patent Title: 4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure
- Patent Title (中): 具有PMOS-NMOS-PMOS-NMOS结构的4晶体管非易失性存储单元
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Application No.: US12751012Application Date: 2010-03-31
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Publication No.: US08213227B2Publication Date: 2012-07-03
- Inventor: Pavel Poplevine , Ernes Ho , Hengyang (James) Lin , Andrew J. Franklin
- Applicant: Pavel Poplevine , Ernes Ho , Hengyang (James) Lin , Andrew J. Franklin
- Applicant Address: US CA Santa Clara
- Assignee: National Semiconductor Corporation
- Current Assignee: National Semiconductor Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G11C16/04
- IPC: G11C16/04 ; G11C11/34
Abstract:
A non-volatile memory (NVM) cell structure comprises a PMOS program transistor having source, drain and bulk region electrodes and a gate electrode that is connected to a data storage node; an NMOS control transistor having source, drain and bulk region electrodes that are commonly-connected to receive a control voltage and a gate electrode that is connected to the data storage node; a PMOS erase transistor having source, drain and bulk region electrodes that are commonly-connected to receive an erase voltage and a gate electrode that is connected to the data storage node; and an NMOS read transistor having source, drain and bulk region electrodes and a gate electrode connected to the data storage node.
Public/Granted literature
- US20110242898A1 4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRUCTURE Public/Granted day:2011-10-06
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