Disclosed are methods and devices, among which is a device that includes a pattern-recognition processor. In some embodiments, the pattern-recognition processor includes a first block of feature cells coupled to a decoder via a first plurality of local input conductors, a first block-disabling circuit, and a plurality of global input conductors. The pattern-recognition processor further includes a second block of feature cells coupled to the decoder via a second plurality of local input conductors, a second block-disabling circuit, and the plurality of global input conductors.