A system including a first clock, a first scan chain, and a first sampling circuit. The first clock is configured to generate a first clock signal. The first scan chain includes a first input, a first set of devices, and a first output. The first input is configured to receive a portion of first data to test the first scan chain. The first set of devices has a first plurality of states, wherein each of the first set of devices changes between the first plurality of states in response to the portion of the first data. The first output is configured to output a portion of second data in response to the first plurality of states. The first sampling circuit is configured to sample the portion of the second data from the first output at least twice per clock cycle of the first clock signal.