A hardware implementation of a QPP interleaved address generator, or QPP interleaver, for use in a QPP turbo decoder uses state machines to determine BCJR engine QPP interleaved row and column addresses used by a soft-bit decoder operating in interleaved half-iteration alpha scan mode or interleaved half-iteration beta scan mode, as well as during non-interleaved half-iterations, if desired. Because QPP interleaving is pseudorandom in nature, the QPP address generator state machines leverage off knowledge of previous row/column addresses generated, as well as knowledge of the maximum row/column dimensions of the systematic soft-bit data store, to reduce the complexity of the processing performed. The described QPP address generator may be implemented in hardware with reduced hardware footprint, reduced power consumption, less heat production and an improved time response. Generated addresses may be provided to BCJR engines directly, or used to retrieve stored systematic soft-bits provided to the respective BCJR engines.