Invention Grant
- Patent Title: Bit error prevention method and information processing apparatus
- Patent Title (中): 位错误预防方法和信息处理装置
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Application No.: US11968964Application Date: 2008-01-03
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Publication No.: US08214720B2Publication Date: 2012-07-03
- Inventor: Shinji Tanaka , Tetsuo Furuichi
- Applicant: Shinji Tanaka , Tetsuo Furuichi
- Applicant Address: JP Osaka-shi
- Assignee: MegaChips Corporation
- Current Assignee: MegaChips Corporation
- Current Assignee Address: JP Osaka-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-028168 20070207
- Main IPC: G11C29/44
- IPC: G11C29/44 ; G11C29/54

Abstract:
Whether the comparison value of temporarily stored data which is read out from a flash memory by a host system exceeds a threshold value related to a bit error or not is checked, and if the comparison value exceeds the threshold value, the temporarily stored data which is read out is rewritten into the flash memory. If the temporarily stored data has an error, the error is corrected by an error correction part and then the data is rewritten. The threshold value includes, e.g., the number of readouts, the number of bit errors and the number of accumulated occurrences of bit errors. The present invention is suitable for prevention of bit errors due to read disturb and can recover the bit data which changes with time, and therefore makes it possible to improve the reliability of the flash memory by preventing occurrence of bit errors.
Public/Granted literature
- US20080189588A1 BIT ERROR PREVENTION METHOD AND INFORMATION PROCESSING APPARATUS Public/Granted day:2008-08-07
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