Invention Grant
- Patent Title: Memory access system
- Patent Title (中): 内存访问系统
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Application No.: US12170102Application Date: 2008-07-09
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Publication No.: US08214725B2Publication Date: 2012-07-03
- Inventor: Takahiko Sugahara
- Applicant: Takahiko Sugahara
- Applicant Address: JP Osaka-shi
- Assignee: MegaChips Corporation
- Current Assignee: MegaChips Corporation
- Current Assignee Address: JP Osaka-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-205651 20070807
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
The Error Correction Code (ECC) circuit generates the first syndrome of write data, which have not been written to the memory. The Error Detection Code (EDC) circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced.
Public/Granted literature
- US20090044076A1 MEMORY ACCESS SYSTEM Public/Granted day:2009-02-12
Information query
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