Invention Grant
- Patent Title: On-chip leakage current modeling and measurement circuit
- Patent Title (中): 片内漏电流建模与测量电路
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Application No.: US12419377Application Date: 2009-04-07
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Publication No.: US08214777B2Publication Date: 2012-07-03
- Inventor: Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
- Applicant: Rajiv V. Joshi , Rouwaida N. Kanj , Jente B. Kuang , Sani R. Nassif
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Stephen R. Tkacs; Stephen J. Walder, Jr.; Libby Z. Toub
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A leakage current monitor circuit provides an accurate statistically representative analog of true off-state leakage current in a digital circuit integrated on a die. At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.
Public/Granted literature
- US20100257492A1 ON-CHIP LEAKAGE CURRENT MODELING AND MEASUREMENT CIRCUIT Public/Granted day:2010-10-07
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