Invention Grant
- Patent Title: Accurate parasitic capacitance extraction for ultra large scale integrated circuits
- Patent Title (中): 超大规模集成电路的精确寄生电容提取
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Application No.: US12893870Application Date: 2010-09-29
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Publication No.: US08214784B2Publication Date: 2012-07-03
- Inventor: Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
- Applicant: Ke-Ying Su , Chia-Ming Ho , Gwan Sin Chang , Chien-Wen Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.
Public/Granted literature
- US20110023003A1 Accurate Parasitic Capacitance Extraction for Ultra Large Scale Integrated Circuits Public/Granted day:2011-01-27
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