Invention Grant
- Patent Title: Method and apparatus to achieve maximum outer level parallelism of a loop
- Patent Title (中): 实现环路最大外层平行度的方法和装置
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Application No.: US11897468Application Date: 2007-08-30
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Publication No.: US08214818B2Publication Date: 2012-07-03
- Inventor: Li Liu , Buqi Cheng , Gansha Wu
- Applicant: Li Liu , Buqi Cheng , Gansha Wu
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F9/45
- IPC: G06F9/45

Abstract:
In one embodiment, the present invention includes a method for constructing a data dependency graph (DDG) for a loop to be transformed, performing statement shifting to transform the loop into a first transformed loop according to at least one of first and second algorithms, performing unimodular and echelon transformations of a selected one of the first or second transformed loops, partitioning the selected transformed loop to obtain maximum outer level parallelism (MOLP), and partitioning the selected transformed loop into multiple sub-loops. Other embodiments are described and claimed.
Public/Granted literature
- US20090064120A1 Method and apparatus to achieve maximum outer level parallelism of a loop Public/Granted day:2009-03-05
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