Invention Grant
- Patent Title: Wafer planarity control between pattern levels
- Patent Title (中): 晶片间平面度控制
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Application No.: US12757665Application Date: 2010-04-09
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Publication No.: US08216945B2Publication Date: 2012-07-10
- Inventor: Steven L. Prins , Brian K. Kirkpatrick , Amitabh Jain
- Applicant: Steven L. Prins , Brian K. Kirkpatrick , Amitabh Jain
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/469 ; H01L21/31
Abstract:
A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.
Public/Granted literature
- US20100261353A1 WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS Public/Granted day:2010-10-14
Information query
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