Invention Grant
- Patent Title: ESD protection device with vertical transistor structure
- Patent Title (中): 具有垂直晶体管结构的ESD保护器件
-
Application No.: US12840749Application Date: 2010-07-21
-
Publication No.: US08217421B2Publication Date: 2012-07-10
- Inventor: Zi-Ping Chen , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
- Applicant: Zi-Ping Chen , Kun-Hsien Lin , Ryan Hsin-Chin Jiang
- Applicant Address: TW Hsin-Chu
- Assignee: Amazing Microelectronic Corp.
- Current Assignee: Amazing Microelectronic Corp.
- Current Assignee Address: TW Hsin-Chu
- Agency: WPAT., P.C.
- Agent Justin King
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.
Public/Granted literature
- US20120018778A1 ESD PROTECTION DEVICE WITH VERTICAL TRANSISTOR STRUCTURE Public/Granted day:2012-01-26
Information query
IPC分类: