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US08217434B2 Semiconductor package having through-electrodes which are electrically connected with internal circuit patterns formed in a semiconductor chip and method for manufacturing the same 有权
具有与形成在半导体芯片中的内部电路图形电连接的贯通电极的半导体封装及其制造方法

Semiconductor package having through-electrodes which are electrically connected with internal circuit patterns formed in a semiconductor chip and method for manufacturing the same
Abstract:
A semiconductor package capable of being efficiently stacked and a method of manufacturing the same is presented. The semiconductor package includes a semiconductor chip, an insulation layer, and a through-electrode. The semiconductor chip has a first surface and a second surface, a circuit section in the semiconductor chip, an internal circuit pattern electrically connected to the circuit section, and a through-hole that passes through the internal circuit pattern and through the first and second surfaces. The insulation layer is on a through-hole of the semiconductor chip and has an opening which exposes the internal circuit pattern which was exposed by the through-hole. The through-electrode is in the through-hole and electrically coupled to the internal circuit pattern which is exposed through the opening of the insulation layer.
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