Invention Grant
US08219341B2 System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) with routing model
有权
使用路由模型实现晶片验收测试(“WAT”)高级过程控制(“APC”)的系统和方法
- Patent Title: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) with routing model
- Patent Title (中): 使用路由模型实现晶片验收测试(“WAT”)高级过程控制(“APC”)的系统和方法
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Application No.: US12411680Application Date: 2009-03-26
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Publication No.: US08219341B2Publication Date: 2012-07-10
- Inventor: Andy Tsen , Sunny Wu , Wang Jo Fei , Jong-I Mou
- Applicant: Andy Tsen , Sunny Wu , Wang Jo Fei , Jong-I Mou
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F19/00
- IPC: G06F19/00

Abstract:
System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.
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