Invention Grant
US08219342B2 Variation tolerant network on chip (NoC) with self-calibrating links
有权
具有自校准链路的可变容错网络芯片（NoC）
- Patent Title: Variation tolerant network on chip (NoC) with self-calibrating links
- Patent Title (中): 具有自校准链路的可变容错网络芯片（NoC）
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Application No.: US12198986Application Date: 2008-08-27
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Publication No.: US08219342B2Publication Date: 2012-07-10
- Inventor: Simone Medardoni , Marcello Lajolo
- Applicant: Simone Medardoni , Marcello Lajolo
- Applicant Address: US NJ Princeton
- Assignee: NEC Laboratories America, Inc.
- Current Assignee: NEC Laboratories America, Inc.
- Current Assignee Address: US NJ Princeton
- Agent Bao Tran; Joseph Kolodka
- Main IPC: G01R35/00
- IPC: G01R35/00
Abstract:
A self correcting device includes a first flip-flop to receive data and coupled to a clock input; one or more delayed flip-flops used to detect delay variations; a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops, a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.
Public/Granted literature
- US20090210184A1 Variation tolerant Network on Chip (NoC) with self-calibrating links Public/Granted day:2009-08-20
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