Invention Grant
US08219754B2 Context instruction cache architecture for a digital signal processor
有权
用于数字信号处理器的上下文指令缓存架构
- Patent Title: Context instruction cache architecture for a digital signal processor
- Patent Title (中): 用于数字信号处理器的上下文指令缓存架构
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Application No.: US12835319Application Date: 2010-07-13
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Publication No.: US08219754B2Publication Date: 2012-07-10
- Inventor: Tushar P. Ringe , Abhijit Giri
- Applicant: Tushar P. Ringe , Abhijit Giri
- Applicant Address: US MA Norwood
- Assignee: Analog Devices, Inc.
- Current Assignee: Analog Devices, Inc.
- Current Assignee Address: US MA Norwood
- Agency: Bingham McCutchen LLP
- Main IPC: G06F13/00
- IPC: G06F13/00
Abstract:
Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, this is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.
Public/Granted literature
- US20110010500A1 Novel Context Instruction Cache Architecture for a Digital Signal Processor Public/Granted day:2011-01-13
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