Invention Grant
US08219831B2 Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration steps
有权
通过在时间常数持续时间步长的处理器流水线的解码阶段通过指令节流来降低温度和功率
- Patent Title: Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration steps
- Patent Title (中): 通过在时间常数持续时间步长的处理器流水线的解码阶段通过指令节流来降低温度和功率
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Application No.: US12361422Application Date: 2009-01-28
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Publication No.: US08219831B2Publication Date: 2012-07-10
- Inventor: Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
- Applicant: Shailender Chaudhry , Quinn A. Jacobson , Marc Tremblay
- Applicant Address: US CA Redwood Shores
- Assignee: Oracle America, Inc.
- Current Assignee: Oracle America, Inc.
- Current Assignee Address: US CA Redwood Shores
- Agency: Fliesler Meyer LLP
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F9/30
Abstract:
A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
Public/Granted literature
- US20100191993A1 LOGICAL POWER THROTTLING Public/Granted day:2010-07-29
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