Invention Grant
US08219879B2 Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same
有权
用于配置低复杂度LDPC解码器和低复杂度LDPC解码器的存储器的方法
- Patent Title: Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same
- Patent Title (中): 用于配置低复杂度LDPC解码器和低复杂度LDPC解码器的存储器的方法
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Application No.: US12707848Application Date: 2010-02-18
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Publication No.: US08219879B2Publication Date: 2012-07-10
- Inventor: Chien-Ming Wu , Ming-Der Shieh , Chun-Ming Huang , Chi-Sheng Lin , Shih-Hao Fang , Shing-Chung Tang
- Applicant: Chien-Ming Wu , Ming-Der Shieh , Chun-Ming Huang , Chi-Sheng Lin , Shih-Hao Fang , Shing-Chung Tang
- Applicant Address: TW Hsinchu
- Assignee: National Chip Implementation Center National Applied Research Laboratories
- Current Assignee: National Chip Implementation Center National Applied Research Laboratories
- Current Assignee Address: TW Hsinchu
- Agency: Stites & Harbison, PLLC
- Agent Juan Carlos A. Marquez, Esq.
- Priority: TW98141975A 20091209
- Main IPC: H03M13/00
- IPC: H03M13/00 ; G11C29/00 ; G06F11/00

Abstract:
A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption.
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