Invention Grant
- Patent Title: CMOS circuit with low-k spacer and stress liner
- Patent Title (中): 具有低k隔离和CMOS应力衬垫的CMOS电路
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Application No.: US12688471Application Date: 2010-01-15
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Publication No.: US08222100B2Publication Date: 2012-07-17
- Inventor: Kangguo Cheng , Bruce B. Doris
- Applicant: Kangguo Cheng , Bruce B. Doris
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Louis J. Percello, Esq.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/40

Abstract:
The present disclosure provides a method of forming a plurality of semiconductor devices, wherein low-k dielectric spacers and a stress inducing liner are applied to the semiconductor devices depending upon the pitch that separates the semiconductor devices. In one embodiment, a first plurality of first semiconductor devices and a second plurality of semiconductor devices is provided, in which each of the first semiconductor devices are separated by a first pitch and each of the second semiconductor devices are separated by a second pitch. The first pitch separating the first semiconductor devices is less than the second pitch separating the second semiconductor devices. A low-k dielectric spacer is formed adjacent to gate structures of the first semiconductor devices. A stress inducing liner is formed on the second semiconductor devices.
Public/Granted literature
- US20110175169A1 CMOS CIRCUIT WITH LOW-K SPACER AND STRESS LINER Public/Granted day:2011-07-21
Information query
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