Invention Grant
- Patent Title: Method of fabricating semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US12760152Application Date: 2010-04-14
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Publication No.: US08222109B2Publication Date: 2012-07-17
- Inventor: Hideo Yamamoto , Kei Takehara
- Applicant: Hideo Yamamoto , Kei Takehara
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Foley & Lardner LLP
- Priority: JP2009-107347 20090427
- Main IPC: H01L21/8242
- IPC: H01L21/8242 ; H01L21/336

Abstract:
A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.
Public/Granted literature
- US20100273304A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2010-10-28
Information query
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