Invention Grant
- Patent Title: Wafer backside grinding with stress relief
- Patent Title (中): 晶圆背面磨削减轻压力
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Application No.: US12335378Application Date: 2008-12-15
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Publication No.: US08222118B2Publication Date: 2012-07-17
- Inventor: Mark Dydyk , Arturo Urquiza , Charles Singleton , Tim McIntosh
- Applicant: Mark Dydyk , Arturo Urquiza , Charles Singleton , Tim McIntosh
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L21/30

Abstract:
A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes.
Public/Granted literature
- US20100151678A1 Wafer Backside Grinding with Stress Relief Public/Granted day:2010-06-17
Information query
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