A transistor and a semiconductor integrated circuit with a reduced layout area. Area reduction of a transistor is realized by arranging contacts at higher density. Specifically, in a transistor including a pair of impurity regions and a gate electrode 604 sandwiched therebetween, one of the impurity regions has respective contact holes (a first contact hole 601 and a second contact hole 602) and the other impurity region has a contact hole (a third contact hole 603), and contacts of the contact holes 601 to 603 or regions 605 to 607 each including a margin for a contact are arranged so as to be a triangular lattice except for the gate electrode 604.