Invention Grant
- Patent Title: DC offset cancellation circuit
- Patent Title (中): DC偏移消除电路
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Application No.: US12950193Application Date: 2010-11-19
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Publication No.: US08222944B2Publication Date: 2012-07-17
- Inventor: Young Jae Lee , Sang Sung Lee , Sang-Gug Lee
- Applicant: Young Jae Lee , Sang Sung Lee , Sang-Gug Lee
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: Rabin & Berdo, P.C.
- Priority: KR10-2009-0112802 20091120; KR10-2010-0026184 20100324
- Main IPC: H03L5/00
- IPC: H03L5/00

Abstract:
A DC offset cancellation circuit includes: a control signal generation unit generating i (i is a natural number) number of pulse signals having a pulse width corresponding to a DC offset amount; a current source supplying i number of currents each having a different current ratio; a switching unit determining a current quantity to be supplied to a feedback capacitor by adjusting a turn-on quantity of each of the i number of currents according to the pulse width of each of the i number of pulse signals; and an electric charge quantity regulation unit charging DC offset electric charges corresponding to current supplied from the switching unit through the feedback capacitor and transferring the DC offset electric charges charged in the feedback capacitor to a sampling capacitor through a rotary capacitor, to allow the sampling capacitor to primarily store the DC offset electric charges and then secondarily store electric charges corresponding to an input signal.
Public/Granted literature
- US20110121880A1 DC OFFSET CANCELLATION CIRCUIT Public/Granted day:2011-05-26
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