Invention Grant
- Patent Title: Boost circuit
- Patent Title (中): 升压电路
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Application No.: US13221311Application Date: 2011-08-30
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Publication No.: US08222953B2Publication Date: 2012-07-17
- Inventor: Hiroshi Nakamura
- Applicant: Hiroshi Nakamura
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-156487 20040526
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
A boost circuit includes: first transistors connected in series between a voltage input node and a voltage output node to constitute a charge transfer circuit; and first capacitors, one ends of which are coupled to the respective connection nodes between the first transistors, the other ends thereof being applied with clocks with plural phases, wherein a gate of a certain stage transistor corresponding to one of the first transistors in the charge transfer circuit is coupled to a drain of another stage transistor corresponding to another one of the first transistors, which is disposed nearer to the voltage output node than the certain stage transistor and driven by the same phase clock as that of the certain stage transistor, the certain stage transistor being disposed nearer to the voltage output node than an initial stage transistor.
Public/Granted literature
- US20110309878A1 BOOST CIRCUIT Public/Granted day:2011-12-22
Information query
IPC分类: