A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage.