Invention Grant
- Patent Title: Semiconductor memory circuit
- Patent Title (中): 半导体存储电路
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Application No.: US13067857Application Date: 2011-06-30
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Publication No.: US08223577B2Publication Date: 2012-07-17
- Inventor: Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
- Applicant: Takesada Akiba , Shigeki Ueda , Toshikazu Tachibana , Masashi Horiguchi
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Stites & Harbison, PLLC
- Agent Juan Carlos A. Marquez, Esq
- Priority: JP2001-261123 20010830
- Main IPC: G11C8/00
- IPC: G11C8/00

Abstract:
The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.
Public/Granted literature
- US20110261639A1 Semiconductor memory circuit Public/Granted day:2011-10-27
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