Invention Grant
US08224614B2 Generating a combination exerciser for executing tests on a circuit
失效
生成组合练习器,用于在电路上执行测试
- Patent Title: Generating a combination exerciser for executing tests on a circuit
- Patent Title (中): 生成组合练习器,用于在电路上执行测试
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Application No.: US12609022Application Date: 2009-10-30
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Publication No.: US08224614B2Publication Date: 2012-07-17
- Inventor: Allon Adir , Maxim Golubev , Andrey Klinger , Amir Nahir
- Applicant: Allon Adir , Maxim Golubev , Andrey Klinger , Amir Nahir
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Glazberg Ziv
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G06F19/00

Abstract:
A first and second test templates are combined to a combination test template. The combination test template may be configured to execute the first and second test templates in combination, and based upon a definition. The combination test template may execute tests in sequential order, concurrently, a combination thereof or the like. The first test template may be configured to be executed by a single-core machine and may be transformed to a multi-core test template that is configured to be executed on a multi-core machine in parallel to other tests. By utilizing the disclosed subject matter, a reduction in overhead of executing the first and second test templates may be achieved; a predetermined interleaving may be performed and a user may control the manner in which the combination test template is executing the first and second test templates. Additionally, reuse of pre-silicon test templates in post-silicon stage may be achieved.
Public/Granted literature
- US20110106482A1 GENERATING A COMBINATION EXERCISER FOR EXECUTING TESTS ON A CIRCUIT Public/Granted day:2011-05-05
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