A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing area as a cache memory included in a semiconductor memory and transfers the data to the host apparatus. The controller performs, when a readout request from the host apparatus satisfies a predetermined condition, at least one of first pre-fetch for reading out, to the first storing area data from a terminal end of a logical address range designated by a readout request being currently processed to a boundary of a logical address aligned in the page unit and a second pre-fetch for reading out data from the boundary of the logical address aligned in the page unit to a next boundary of the logical address.