Invention Grant
- Patent Title: Semiconductor testing apparatus and method
- Patent Title (中): 半导体测试仪器及方法
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Application No.: US13081189Application Date: 2011-04-06
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Publication No.: US08225149B2Publication Date: 2012-07-17
- Inventor: Akihiro Hirota
- Applicant: Akihiro Hirota
- Applicant Address: JP
- Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee Address: JP
- Agency: Studebaker & Brackett PC
- Agent Donald R. Studebaker
- Priority: JP2007-254362 20070928
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened.
Public/Granted literature
- US20110185239A1 SEMICONDUCTOR TESTING APPARATUS AND METHOD Public/Granted day:2011-07-28
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