Invention Grant
US08225157B2 Shadow protocol circuit having full and reduced pin select outputs 有权
阴影协议电路具有完整和降低的引脚选择输出

  • Patent Title: Shadow protocol circuit having full and reduced pin select outputs
  • Patent Title (中): 阴影协议电路具有完整和降低的引脚选择输出
  • Application No.: US13078621
    Application Date: 2011-04-01
  • Publication No.: US08225157B2
    Publication Date: 2012-07-17
  • Inventor: Lee D. Whetsel
  • Applicant: Lee D. Whetsel
  • Applicant Address: US TX Dallas
  • Assignee: Texas Instruments Incorporated
  • Current Assignee: Texas Instruments Incorporated
  • Current Assignee Address: US TX Dallas
  • Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
  • Main IPC: G01R31/28
  • IPC: G01R31/28
Shadow protocol circuit having full and reduced pin select outputs
Abstract:
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
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